R5F72115D160FPV datasheet(174/1228 Pages) RENESAS

174 / 1228 page

Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 150 of 1200

REJ09B0344-0200

7.3.4

Break Address Register_1 (BAR_1)

BAR_1 is a 32-bit readable/writable register. BAR_1 specifies the address used as a break

condition in channel 1. The control bits CD1_1 and CD1_0 in the break bus cycle register_1

(BBR_1) select one of the three address buses for a break condition of channel 1. BAR_1 is

initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or

in software standby mode or sleep mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BA1_31 BA1_30 BA1_29 BA1_28 BA1_27 BA1_26 BA1_25 BA1_24 BA1_23 BA1_22 BA1_21 BA1_20 BA1_19 BA1_18 BA1_17 BA1_16

BA1_15 BA1_14 BA1_13 BA1_12 BA1_11 BA1_10 BA1_9 BA1_8 BA1_7 BA1_6 BA1_5 BA1_4 BA1_3 BA1_2 BA1_1 BA1_0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BA1_31 to

BA1_0

All 0

R/W

Break Address 1

Store an address on the CPU address bus (FAB or

MAB) or IAB specifying break conditions of channel 1.

When the C bus and instruction fetch cycle are

selected by BBR_1, specify an FAB address in bits

BA1_31 to BA1_0.

When the C bus and data access cycle are selected by

BBR_1, specify an MAB address in bits BA1_31 to

BA1_0.

Note:

When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_1 to 0.

R5F72115D160FPV Datasheet(PDF) 174 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 174 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL