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R5F72115D160FPV Datasheet(PDF) 175 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 175 Page - Renesas Technology Corp

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Section 7 User Break Controller (UBC)
Rev. 2.00 May. 08, 2008 Page 151 of 1200
REJ09B0344-0200
7.3.5
Break Address Mask Register_1 (BAMR_1)
BAMR_1 is a 32-bit readable/writable register. BAMR_1 specifies bits masked in the break
address bits specified by BAR_1. BAMR_1 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
BAM1_31 BAM1_30 BAM1_29 BAM1_28 BAM1_27 BAM1_26 BAM1_25 BAM1_24 BAM1_23 BAM1_22 BAM1_21 BAM1_20 BAM1_19 BAM1_18 BAM1_17 BAM1_16
BAM1_15 BAM1_14 BAM1_13 BAM1_12 BAM1_11 BAM1_10 BAM1_9
BAM1_8
BAM1_7
BAM1_6
BAM1_5
BAM1_4
BAM1_3
BAM1_2
BAM1_1
BAM1_0
Bit
Bit Name
Initial
Value
R/W
Description
31 to 0
BAM1_31 to
BAM1_0
All 0
R/W
Break Address Mask 1
Specify bits masked in the channel-1 break address
bits specified by BAR_1 (BA1_31 to BA1_0).
0: Break address bit BA1_n is included in the break
condition
1: Break address bit BA1_n is masked and not
included in the break condition
Note:
n = 31 to 0



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