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R5F72115D160FPV Datasheet(PDF) 171 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 171 Page - Renesas Technology Corp

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Section 7 User Break Controller (UBC)
Rev. 2.00 May. 08, 2008 Page 147 of 1200
REJ09B0344-0200
7.3.2
Break Address Mask Register_0 (BAMR_0)
BAMR_0 is a 32-bit readable/writable register. BAMR_0 specifies bits masked in the break
address bits specified by BAR_0. BAMR_0 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
BAM0_31 BAM0_30 BAM0_29 BAM0_28 BAM0_27 BAM0_26 BAM0_25 BAM0_24 BAM0_23 BAM0_22 BAM0_21 BAM0_20 BAM0_19 BAM0_18 BAM0_17 BAM0_16
BAM0_15 BAM0_14 BAM0_13 BAM0_12 BAM0_11 BAM0_10 BAM0_9
BAM0_8
BAM0_7
BAM0_6
BAM0_5
BAM0_4
BAM0_3
BAM0_2
BAM0_1
BAM0_0
Bit
Bit Name
Initial
Value
R/W
Description
31 to 0
BAM0_31 to
BAM0_0
All 0
R/W
Break Address Mask 0
Specify bits masked in the channel-0 break address
bits specified by BAR_0 (BA0_31 to BA0_0).
0: Break address bit BA0_n is included in the break
condition
1: Break address bit BA0_n is masked and not
included in the break condition
Note:
n = 31 to 0



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