R5F72115D160FPV datasheet(197/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 173 of 1200

REJ09B0344-0200

7.5

Usage Notes

1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the

period from executing an instruction to rewrite the UBC register till the new value is actually

rewritten, the desired break may not occur. In order to know the timing when the UBC register

is changed, read from the last written register. Instructions after then are valid for the newly

written register value.

2. The UBC cannot monitor access to the C bus and I bus cycles in the same channel.

3. When a user break interrupt request and another exception source occur at the same

instruction, which has higher priority is determined according to the priority levels defined in

table 5.1 in section 5, Exception Handling. If an exception source with higher priority occurs,

the user break interrupt request is not received.

4. Note the following when a break occurs in a delay slot.

If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not

received immediately before execution of the branch destination.

5. User breaks are disabled during UBC module standby mode. Do not read from or write to the

UBC registers during UBC module standby mode; the values are not guaranteed.

6. Do not set an address within an interrupt exception handling routine whose interrupt priority

level is at least 15 (including user break interrupts) as a break address.

7. Do not set break after instruction execution for the SLEEP instruction or for the delayed

branch instruction where the SLEEP instruction is placed at its delay slot.

8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are

placed. If the address of the lower 16 bits is set and a break before instruction execution is set

as a break condition, the break is handled as a break after instruction execution.

9. Do not set a user break before instruction execution for the instruction following the DIVU or

DIVS instruction. If a user break before instruction execution is set for the instruction

following the DIVU or DIVS instruction and an exception or interrupt occurs during execution

of the DIVU or DIVS instruction, a user break occurs before instruction execution even though

execution of the DIVU or DIVS instruction is halted.

10. Do not set a user break both before instruction execution and after instruction execution for

instruction of the same address. If, for example, a user break before instruction execution on

channel 0 and a user break after instruction on channel 1 are set at the instruction of the same

address, the condition match flag for the channel 1 is set even though a user break on channel 0

occurs before instruction execution.

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