R5F72115D160FPV datasheet(199/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 175 of 1200

REJ09B0344-0200

Section 8 Bus State Controller (BSC)

The bus state controller (BSC) outputs control signals for various types of memory that is

connected to the external address space and external devices. BSC functions enable this LSI to

connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.

8.1

Features

The BSC has the following features.

1. External address space

⎯ A maximum of 64 Mbytes for each of areas CS0 to CS7.

⎯ Can specify the normal space interface, SRAM interface with byte selection, burst ROM

(clock synchronous or asynchronous), MPX-I/O, and SDRAM for each address space.

⎯ Can select the data bus width (8 or 16 bits) for each address space.

⎯ Controls insertion of wait cycles for each address space.

⎯ Controls insertion of wait cycles for each read access and write access.

⎯ Can set independent idle cycles during the continuous access for five cases: read-write (in

same space/different spaces), read-read (in same space/different spaces), the first cycle is a

write access.

2. Normal space interface

⎯ Supports the interface that can directly connect to the SRAM.

3. Burst ROM interface (clock asynchronous)

⎯ High-speed access to the ROM that has the page mode function.

4. MPX-I/O interface

⎯ Can directly connect to a peripheral LSI that needs an address/data multiplexing.

5. SDRAM interface

⎯ Can set the SDRAM in up to two areas.

⎯ Multiplex output for row address/column address.

⎯ Efficient access by single read/single write.

⎯ High-speed access in bank-active mode.

⎯ Supports an auto-refresh and self-refresh.

⎯ Supports low-frequency and power-down modes.

⎯ Issues MRS and EMRS commands.

R5F72115D160FPV Datasheet(PDF) 199 Page - Renesas Technology Corp