R5F72115D160FPV datasheet(202/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 178 of 1200

REJ09B0344-0200

8.2

Input/Output Pins

Table 8.1 shows the pin configuration of the BSC.

Table 8.1

Pin Configuration

Name

I/O

Function

A25 to A0

Output

Address bus

D15 to D0

I/O

Data bus

Output

Bus cycle start

CS0 to CS7

Output

Chip select

RD/

Output

Read/write

Connects to

WE pins when SDRAM or SRAM with byte selection is

connected.

Output

Read pulse signal (read data output enable signal)

Functions as a strobe signal for indicating memory read cycles when

PCMCIA is used.

Output

A signal used to hold an address when MPX-I/O is in use

WE1/DQMLU Output

Indicates that D15 to D8 are being written to.

Connected to the byte select signal when a SRAM with byte selection is

connected.

Functions as the select signals for D15 to D8 when SDRAM is

connected.

WE0/DQMLL Output

Indicates that D7 to D0 are being written to.

Connected to the byte select signal when a SRAM with byte selection is

connected.

Functions as the select signals for D7 to D0 when SDRAM is connected.

RASL

Output

Connects to

RAS pin when SDRAM is connected.

CASL

Output

Connects to

CAS pin when SDRAM is connected.

CKE

Output

Connects to CKE pin when SDRAM is connected.

WAIT

Input

External wait input

BREQ

Input

Bus request input

BACK

Output

Bus enable output

REFOUT

Output

Refresh request output in bus-released state

MD1, MD0

Input

Select bus width (8 or 16 bits) of area 0 and modes including

enabling/disabling of the on-chip ROM.

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