R5F72115D160FPV datasheet(205/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 181 of 1200

REJ09B0344-0200

In on-chip ROM-disabled mode, the LSI is activated by the program stored in the external

memory allocated to area 0. The second half of area 0 is the external memory space. In this

case, a ROM is assumed for the external memory of area 0. Therefore, minimum functions are

provided for the pins including address bus, data bus, CS0, and RD. Although BS, RDWR,

WEn, and other pins are shown in the examples of access waveforms in this section, these are

examples when pin settings are performed by the pin function controller. For details, see

section 19, Pin Function Controller (PFC). Do not perform any operation except for area 0 read

access until the pin settings by the program is completed.

• Initial Settings of Data Bus Widths for Areas 0 to 7

The initial settings of data bus widths of areas 0 to 7 can be selected at a time as 8 or 16 bits.

In on-chip ROM-disabled mode, the data bus width of area 0 cannot be changed from its initial

setting after a power-on reset, but the data bus widths of areas 1 to 7 can be changed by

areas 0 to 7 can be changed by register settings in the program. Note that data bus widths will

be restricted depending on memory types.

• Initial Settings of Endianness

The initial settings of byte-data alignment of areas 0 to 7 can be selected as big endian or little

endian. In on-chip ROM-disabled mode, the endianness of area 0 cannot be changed from its

initial setting after a power-on reset, but the endianness of areas 1 to 7 can be changed by

to 7 can be changed by register settings in the program. Little endian cannot be selected in area

0. Since both 32-bit and 16-bit accesses are included in instruction fetches, no instructions can

be assigned in little endian area. Accordingly, instructions should be executed in big endian

area.

For details of mode settings, see section 3, MCU Operating Modes.

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