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R5F72115D160FPV Datasheet(PDF) 209 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 209 Page - Renesas Technology Corp |
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209 / 1228 page ![]() Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 185 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 3 ⎯ 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 HIZCKIO 0 R/W High-Z CK Control Specifies the state in CK standby mode and when bus mastership is released. 0: CK is in high impedance state in standby mode and bus-released state. 1: CK is driven in standby mode and bus-released state. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in standby mode for A25 to A0, BS, CSn, RD/WR, WEn/DQMxx, AH, and RD. At bus- released state, these pins are in high-impedance state regardless of the setting value of the HIZMEM bit. 0: High impedance in standby mode. 1: Driven in standby mode 0 HIZCNT 0 R/W High-Z Control Specifies the state in standby mode and bus-released state for CKE, RASL, and CASL. 0: CKE, RASL, and CASL are in high-impedance state in standby mode and bus-released state. 1: CKE, RASL, and CASL are driven in standby mode and bus-released state. |
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