R5F72115D160FPV datasheet(210/1228 Pages) RENESAS

210 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 186 of 1200

REJ09B0344-0200

8.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)

CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a

space, data bus width of an area, endian, and the number of waits between access cycles. This

and in software standby mode.

Do not access external memory other than area 0 until CSnBCR initial setting is completed.

Idle cycles may be inserted even when they are not specified. For details, see section 8.5.10, Wait

between Access Cycles.

0011011011011011

R/W

00000

000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

CSnBCR samples the external pins (MD1 and MD0) that specify the bus width at power-on reset.

IWW[2:0]

IWRWD[2:0]

IWRWS[2:0]

IWRRD[2:0]

IWRRS[2:0]

TYPE[2:0]

ENDIAN

BSZ[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

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