R5F72115D160FPV datasheet(214/1228 Pages) RENESAS

214 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 190 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

10, 9

BSZ[1:0]

11*

R/W

Data Bus Width Specification

Specify the data bus widths of spaces.

00: Reserved (setting prohibited)

01: 8-bit size

10: 16-bit size

11: Reserved (setting prohibited)

For MPX-I/O, selects bus width by address

Notes:

1. If area 5 is specified as MPX-I/O, the bus

width can be specified as 8 bits or 16 bits

by the address according to the SZSEL bit

in CS5WCR by specifying the BSZ[1:0]

bits to 11. The fixed bus width can be

specified as 8 bits or 16 bits.

2. The initial data bus width for areas 0 to 7

is specified by external pins. In on-chip

ROM-disabled mode, writing to the BSZ1

and BSZ0 bits in CS0BCR is ignored, but

the bus width settings in CS1BCR to

CS7BCR can be modified. In on-chip

ROM-enabled mode, the bus width

settings in CS0BCR to CS7BCR can be

modified.

3. If area 2 or area 3 is specified as SDRAM

space, the bus width can be specified as

16 bits only.

4. If area 0 or 4 is specified as clock-

synchronous burst ROM space, the bus

width can be specified as 16 bits only.

8 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

CSnBCR samples the external pins (MD1 and MD0) that specify the bus width at

power-on reset.

R5F72115D160FPV Datasheet(PDF) 214 Page - Renesas Technology Corp

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