R5F72115D160FPV datasheet(218/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 194 of 1200

REJ09B0344-0200

• CS1WCR, CS7WCR

0000000000000000

R/W

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

BAS

WW[2:0]

SW[1:0]

WR[3:0]

HW[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS

R/W

SRAM with Byte Selection Byte Access Select

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read/write timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

18 to 16

WW[2:0]

000

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for

write access.

000: The same cycles as WR[3:0] setting (number of

read access wait cycles)

001: No cycle

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

R5F72115D160FPV Datasheet(PDF) 218 Page - Renesas Technology Corp

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