R5F72115D160FPV datasheet(217/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 193 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait input is valid

1: External wait input is ignored

5 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

HW[1:0]

R/W

Delay Cycles from RD,

WEn Negation to Address, CS0

Negation

Specify the number of delay cycles from RD and

WEn

negation to address and

CS0 negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

Note

To connect the burst ROM to the CS0 space and switch to the burst ROM interface

after activation in ROM-disabled mode, set the TYPE[2:0] bits in CS0BCR after setting

the burst number by the bits 20 and 21 and the burst wait cycle number by the bits16

and 17. Do not write 1 to the reserved bits other than above bits.

R5F72115D160FPV Datasheet(PDF) 217 Page - Renesas Technology Corp

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