R5F72115D160FPV datasheet(216/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

216 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 192 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

19 to 13

⎯ *

All 0

R/W

Reserved

Set these bits to 0 when the interface for normal space

or SRAM with byte selection is used.

12, 11

SW[1:0]

R/W

Number of Delay Cycles from Address,

CS0 Assertion

RD, WEn Assertion

Specify the number of delay cycles from address and

CS0 assertion to RD and WEn assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

10 to 7

WR[3:0]

1010

R/W

Number of Access Wait Cycles

Specify the number of cycles that are necessary for

read/write access.

0000: No cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R5F72115D160FPV Datasheet(PDF) 216 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 216 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL