R5F72115D160FPV datasheet(204/1228 Pages) RENESAS

204 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 180 of 1200

REJ09B0344-0200

Table 8.3

Address Map in On-Chip ROM-Disabled Mode

Address

Space

Memory to be Connected

Size

H'0000 0000 to H'03FF FFFF

CS0

Normal space, SRAM with byte selection,

burst ROM (asynchronous or synchronous)

64 Mbytes

H'0400 0000 to H'07FF FFFF

CS1

Normal space, SRAM with byte selection

64 Mbytes

H'0800 0000 to H'0BFF FFFF

CS2

Normal space, SRAM with byte selection,

SDRAM

64 Mbytes

H'0C00 0000 to H'0FFF FFFF

CS3

Normal space, SRAM with byte selection,

SDRAM

64 Mbytes

H'1000 0000 to H'13FF FFFF

CS4

Normal space, SRAM with byte selection,

burst ROM (asynchronous)

64 Mbytes

H'1400 0000 to H'17FF FFFF

CS5

Normal space, SRAM with byte selection,

MPX-I/O

64 Mbytes

H'1800 0000 to H'1BFF FFFF

CS6

Normal space, SRAM with byte selection

64 Mbytes

H'1C00 0000 to H'1FFF FFFF

CS7

Normal space, SRAM with byte selection

64 Mbytes

H'2000 0000 to H'FFF7 FFFF

Other

Reserved area

⎯

H'FFF8 0000 to H'FFFB FFFF

Other

On-chip RAM, reserved area*

⎯

H'FFFC 0000 to H'FFFF FFFF

Other

On-chip peripheral modules, reserved area*

⎯

Note:

For the on-chip RAM space, access the addresses shown in section 22, On-Chip RAM.

For the on-chip I/O register space, access the addresses shown in section 26, List of

Registers. Do not access addresses which are not described in these sections.

Otherwise, the correct operation cannot be guaranteed.

8.3.2

Setting Operating Modes

This LSI can set the following modes of operation at the time of power-on reset using the external

pins.

• Single-Chip Mode

In single-chip mode, no access is made to the external bus, and the LSI is activated by the on-

chip ROM program upon a power-on reset. The BSC module enters the module standby state

to reduce power consumption.

• On-Chip ROM-Enabled Mode/On-Chip ROM-Disabled Mode

In on-chip ROM-enabled mode, since the first half of area 0 is allocated to the on-chip ROM,

the LSI can be activated by the on-chip ROM program upon a power-on reset. The second half

of area 0 is the external memory space.

R5F72115D160FPV Datasheet(PDF) 204 Page - Renesas Technology Corp

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