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R5F72115D160FPV Datasheet(PDF) 201 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 201 Page - Renesas Technology Corp |
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201 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 177 of 1200 REJ09B0344-0200 Figure 8.1 shows a block diagram of the BSC. CMNCR CS0WCR CS7WCR CS0BCR CS7BCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller Wait controller Area controller Memory controller Refresh controller [Legend] BSC CS0 to CS7 REFOUT WAIT MD1, MD0 A25 to A0, D15 to D0 BACK BREQ BS, RD/WR, RD, WE1, WE0, RASL, CASL CKE, DQMxx, AH, CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0 to 7) CSn space bus control register (n = 0 to 7) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Figure 8.1 Block Diagram of BSC |
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