R5F72115D160FPV datasheet(227/1228 Pages) RENESAS

227 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 203 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

MPXW

R/W

MPX-I/O Interface Address Wait

This bit setting is valid only when area 5 is specified as

MPX-I/O. Specifies the address cycle insertion wait for

MPX-I/O interface.

0: Inserts no wait cycle

1: Inserts 1 wait cycle

BAS

R/W

SRAM with Byte Selection Byte Access Select

This bit setting is valid only when area 5 is specified as

SRAM with byte selection.

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read access cycle

and asserts the RD/

WR signal at the write timing.

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

18 to 16

WW[2:0]

000

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for

write access.

000: The same cycles as WR[3:0] setting (number of

read access wait cycles)

001: No cycle

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to 13

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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