R5F72115D160FPV datasheet(230/1228 Pages) RENESAS

230 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 206 of 1200

REJ09B0344-0200

• CS6WCR

0000000000000000

RRRRRRRRRRR

R/W

RRRR

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

BAS

----

SW[1:0]

WR[3:0]

HW[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS

R/W

SRAM with Byte Selection Byte Access Select

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

19 to 13

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

12, 11

SW[1:0]

R/W

Number of Delay Cycles from Address,

CS6 Assertion

RD, WEn Assertion

Specify the number of delay cycles from address,

CS6

assertion to

RD and WEn assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

R5F72115D160FPV Datasheet(PDF) 230 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 230 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL