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R5F72115D160FPV Datasheet(PDF) 232 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 232 Page - Renesas Technology Corp |
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232 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 208 of 1200 REJ09B0344-0200 (2) Burst ROM (Clock Asynchronous) • CS0WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R R R R R/W R/W R R R/W R/W 0000010100000000 R R R R R R/W R/W R/W R/W R/W R R R R R R Bit: Initial value: R/W: Bit: Initial value: R/W: ---------- BST[1:0] - - BW[1:0] - - - - - W[3:0] WM - - - - - - Bit Bit Name Initial Value R/W Description 31 to 22 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width BST[1:0] Burst count 00 16 burst × one time 8 bits 01 4 burst × four times 00 8 burst × one time 01 2 burst × four times 16 bits 10 4-4 or 2-4-2 burst 21, 20 BST[1:0] 00 R/W 19, 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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