R5F72115D160FPV datasheet(231/1228 Pages) RENESAS

231 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 207 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

10 to 7

WR[3:0]

1010

R/W

Number of Access Wait Cycles

Specify the number of cycles that are necessary for

read/write access.

0000: No cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification of this bit is valid even when the

number of access wait cycles is 0.

0: The external wait input is valid

1: The external wait input is ignored

5 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

HW[1:0]

R/W

Number of Delay Cycles from

RD, WEn Negation to

Address,

CS6 Negation

Specify the number of delay cycles from

RD, WEn

negation to address, and

CS6 negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

R5F72115D160FPV Datasheet(PDF) 231 Page - Renesas Technology Corp

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