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R5F72115D160FPV Datasheet(PDF) 257 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 257 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 233 of 1200
REJ09B0344-0200
read in case of a 16-bit device. When writing, only the
WEn signal for the byte to be written is
asserted.
It is necessary to output the data that has been read using
RD when a buffer is established in the
data bus. The RD/
WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 8.3 and 8.4 show the basic timings of normal space access. If the WM bit in CSnWCR is
cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait
(figure 8.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is
inserted (figure 8.4).
CK
A25 to A0
RD
RD/
WR
D15 to D0
WEn
D15 to D0
DACKn
BS
WAIT
CSn
T1
T2
Tnop
T1
T2
Read
Write
*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.3 Continuous Access for Normal Space 1
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0
(Access Wait = 0, Cycle Wait = 0)



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