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R5F72115D160FPV Datasheet(PDF) 260 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 260 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 236 of 1200
REJ09B0344-0200
8.5.3
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 1, 4, 5, and 7 to insert wait cycles independently in read
access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write
cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access
shown in figure 8.7.
T1
CK
A25 to A0
CSn
RD/
WR
RD
D15 to D0
WEn
D15 to D0
BS
Tw
Read
Write
T2
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.7 Wait Timing for Normal Space Access (Software Wait Only)



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