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R5F72115D160FPV Datasheet(PDF) 263 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 263 Page - Renesas Technology Corp |
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263 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 239 of 1200 REJ09B0344-0200 8.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous access cycles. Address output is increased to 3 cycles by setting the MPXW bit in CS5WCR to 1. The RD/ WR signal is output at the same time as the CS5 signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. Timing charts are shown in figures 8.10 to 8.12. |
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