R5F72115D160FPV datasheet(267/1228 Pages) RENESAS

267 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 243 of 1200

REJ09B0344-0200

8.5.6

SDRAM Interface

(1)

SDRAM Direct Connection

The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,

8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in

read and write command cycles.

The control signals for direct connection of SDRAM are

RASL, CASL, RD/WR, DQMUL,

DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas,

and signals other than CKE are valid when

CS2 or CS3 is asserted. SDRAM can be connected to

up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 16 bits

only.

Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as

SDRAM operating mode.

Commands for SDRAM can be specified by

RASL, CASL, RD/WR, and specific address signals.

These commands supports:

• NOP

• Auto-refresh (REF)

• Self-refresh (SELF)

• All banks pre-charge (PALL)

• Specified bank pre-charge (PRE)

• Bank active (ACTV)

• Read (READ)

• Read with pre-charge (READA)

• Write (WRIT)

• Write with pre-charge (WRITA)

• Write mode register (MRS, EMRS)

The byte to be accessed is specified by

DQMUL and DQMLL. Reading or writing is performed

for a byte whose corresponding

DQMxx is low. For details on the relationship between DQMxx

and the byte to be accessed, see section 8.5.1, Endian/Access Size and Data Alignment.

Figure 8.13 shows an example of the connection of the SDRAM with the LSI.

R5F72115D160FPV Datasheet(PDF) 267 Page - Renesas Technology Corp