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R5F72115D160FPV Datasheet(PDF) 270 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 270 Page - Renesas Technology Corp |
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270 / 1228 page ![]() Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 246 of 1200 REJ09B0344-0200 Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22* 2 A22* 2 A13 (BA1) A13 A21* 2 A21* 2 A12 (BA0) Specifies bank A12 A20 A12 A11 Address A11 A19 L/H* 1 A10/AP Specifies address/precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to access the mode. 2. Bank address specification |
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