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R5F72115D160FPV Datasheet(PDF) 272 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 272 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 248 of 1200
REJ09B0344-0200
Table 8.10
Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
01 (12 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin
Function
A17
A27
A17
A16
A26
A16
A15
A25
A15
Unused
A14
A24*
2
A24*
2
A13 (BA1)
A13
A23*
2
A23*
2
A12 (BA0)
Specifies bank
A12
A22
A12
A11
Address
A11
A21
L/H*
1
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
Address
A0
A10
A0
Unused
Example of connected memory
256-Mbit product (4 Mwords
× 16 bits × 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification



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