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R5F72115D160FPV Datasheet(PDF) 276 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 276 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 252 of 1200
REJ09B0344-0200
be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit
between this LSI and the SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.
Tc4
CK
A25 to A0
CSn
RD/
WR
RASL, RASU
DQMxx
D15 to D0
BS
(Tap)
DACKn*2
Tr
Tc2
Tc3
Tc1
Td4
Tde
Td2
Td3
Td1
A12/A11*1
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.14 Burst Read Basic Timing (CAS Latency 1, Auto-Precharge)



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