R5F72115D160FPV datasheet(256/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 232 of 1200

REJ09B0344-0200

8.5.2

Normal Space Interface

(1)

Basic Timing

For access to a normal space, this LSI uses strobe signal output in consideration of the fact that

mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see

section 8.5.8, SRAM Interface with Byte Selection. Figure 8.2 shows the basic timings of normal

space access. A no-wait normal access is completed in two cycles. The

BS signal is asserted for

one cycle to indicate the start of a bus cycle.

Note: * The waveform for DACKn is when active low is specified.

A25 to A0

RD/

D15 to D0

DACKn

CSn

WEn

D15 to D0

Read

Write

Figure 8.2 Normal Space Basic Access Timing (Access Wait 0)

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 16 bits are always

R5F72115D160FPV Datasheet(PDF) 256 Page - Renesas Technology Corp