R5F72115D160FPV datasheet(252/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 228 of 1200

REJ09B0344-0200

8.4.7

Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1

and RTCNT is cleared to 0.

When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.

This request is maintained until the refresh operation is performed. If the request is not processed

when the next matching occurs, the previous request is ignored.

The

REFOUT signal can be asserted when a refresh request is generated while the bus is released.

For details, see the description of Relationship between Refresh Requests and Bus Cycles in

section 8.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 8.5.11, Bus

Arbitration.

When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal.

The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit

only affects the interrupt request and does not clear the refresh request. Therefore, a combination

of refresh request and interval timer interrupt can be specified so that the number of refresh

requests are counted by using timer interrupts while refresh is performed periodically.

When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write

protection. This register is initialized to H'00000000 by a power-on reset and retains the value by a

manual reset and in software standby mode.

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

----------------

--------

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8

⎯

All 0

Reserved

These bits are always read as 0.

7 to 0

All 0

R/W

8-Bit Register

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