R5F72115D160FPV datasheet(249/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 225 of 1200

REJ09B0344-0200

8.4.5

Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM. RTCSR is initialized to H'00000000 by

a power-on reset and retains the value by a manual reset and in software standby mode.

When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write

protection.

The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is

adjusted only by a power-on reset. Note that there is an error in the time until the compare match

flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value

other than B'000.

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

----------------

CMF

CMIE

CKS[2:0]

RRC[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8

⎯

All 0

Reserved

These bits are always read as 0.

CMF

R/W

Compare Match Flag

Indicates that a compare match occurs between the

refresh timer counter (RTCNT) and refresh time

constant register (RTCOR). This bit is set or cleared in

the following conditions.

0: Clearing condition: When 0 is written in CMF after

reading out RTCSR during CMF = 1.

1: Setting condition: When the condition RTCNT =

RTCOR is satisfied.

R5F72115D160FPV Datasheet(PDF) 249 Page - Renesas Technology Corp

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