R5F72115D160FPV datasheet(246/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 222 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

15, 14

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DEEP

R/W

Deep Power-Down Mode

This bit is valid for low-power SDRAM. If the RFSH or

RMODE bit is set to 1 while this bit is set to 1, the deep

power-down entry command is issued and the low-

power SDRAM enters deep power-down mode.

0: Self-refresh mode

1: Deep power-down mode

SLOW

R/W

Low-Frequency Mode

Specifies the output timing of command, address, and

write data for SDRAM and the latch timing of read data

from SDRAM. Setting this bit makes the hold time for

command, address, write and read data extended for

half cycle (output or read at the falling edge of CK).

This mode is suitable for SDRAM with low-frequency

clock.

0: Command, address, and write data for SDRAM is

output at the rising edge of CK. Read data from

SDRAM is latched at the rising edge of CK.

1: Command, address, and write data for SDRAM is

output at the falling edge of CK. Read data from

SDRAM is latched at the falling edge of CK.

RFSH

R/W

Refresh Control

Specifies whether or not the refresh operation of the

SDRAM is performed.

0: No refresh

1: Refresh

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