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R5F72115D160FPV Datasheet(PDF) 242 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 242 Page - Renesas Technology Corp |
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242 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 218 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 1, 0 WTRC[1:0]* 00 R/W Number of Idle Cycles from REF Command/Self- Refresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below. • From the issuance of the REF command until the issuance of the ACTV/REF/MRS command • From releasing self-refresh until the issuance of the ACTV/REF/MRS command. The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. |
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