R5F72115D160FPV datasheet(238/1228 Pages) RENESAS

238 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 214 of 1200

REJ09B0344-0200

(3)

SDRAM*

• CS2WCR

0000000000000000

RRRRRRRRRRRRRRRR

0000010100000000

RRRRRRR

R/W

RRRRRRR

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

----------------

A2CL[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 11

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

⎯

Reserved

This bit is always read as 1. The write value should

always be 1.

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

8, 7

A2CL[1:0]

R/W

CAS Latency for Area 2

Specify the CAS latency for area 2.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: 4 cycles

6 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2

as normal space or SRAM with byte selection.

R5F72115D160FPV Datasheet(PDF) 238 Page - Renesas Technology Corp

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