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R5F72115D160FPV Datasheet(PDF) 240 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 240 Page - Renesas Technology Corp |
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240 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 216 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 12 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0] 01 R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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