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R5F72115D160FPV Datasheet(PDF) 243 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 243 Page - Renesas Technology Corp |
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243 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 219 of 1200 REJ09B0344-0200 (4) Burst ROM (Clock Synchronous) • CS0WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 RRRRRRRRRRRRRR R/W R/W 0000010100000000 R R R R R R/W R/W R/W R/W R/W R R R R R R Bit: Initial value: R/W: Bit: Initial value: R/W: -------------- BW[1:0] ----- W[3:0] WM - - - - - - Bit Bit Name Initial Value R/W Description 31 to 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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