R5F72115D160FPV datasheet(245/1228 Pages) RENESAS

245 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 221 of 1200

REJ09B0344-0200

8.4.4

SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be

connected.

SDCR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and

in software standby mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

A2ROW[1:0]

A3ROW[1:0]

A2COL[1:0]

A3COL[1:0]

DEEP

SLOW

RFSH RMODEPDOWN BACTV

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

20, 19

A2ROW[1:0] 00

R/W

Number of Bits of Row Address for Area 2

Specify the number of bits of row address for area 2.

00: 11 bits

01: 12 bits

10: 13 bits

11: Reserved (setting prohibited)

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

17, 16

A2COL[1:0]

R/W

Number of Bits of Column Address for Area 2

Specify the number of bits of column address for

area 2.

00: 8 bits

01: 9 bits

10: 10 bits

11: Reserved (setting prohibited)

R5F72115D160FPV Datasheet(PDF) 245 Page - Renesas Technology Corp

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