R5F72115D160FPV datasheet(239/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 215 of 1200

REJ09B0344-0200

• CS3WCR

0000000000000000

RRRRRRRRRRRRRRRR

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are

used in both areas in common.

----------------

WTRP[1:0]*

WTRCD[1:0]*

TRWL[1:0]*

WTRC[1:0]*

A3CL[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

14, 13

WTRP[1:0]*

R/W

Number of Auto-Precharge Completion Wait Cycles

Specify the number of minimum precharge completion

wait cycles as shown below.

• From the start of auto-precharge and issuing of

ACTV command for the same bank

• From issuing of the PRE/PALL command to issuing

of the ACTV command for the same bank

• Till entering power-down mode or deep power-

down mode

• From the issuing of PALL command to issuing REF

command in auto-refresh mode

• From the issuing of PALL command to issuing

SELF command in self-refresh mode

The setting for areas 2 and 3 is common.

00: No cycle

01: 1 cycle

10: 2 cycles

11: 3 cycles

R5F72115D160FPV Datasheet(PDF) 239 Page - Renesas Technology Corp

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