R5F72115D160FPV datasheet(293/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 269 of 1200

REJ09B0344-0200

(9)

Relationship between Refresh Requests and Bus Cycles

If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle

to be completed. If a refresh request occurs while the bus is released by the bus arbitration

function, the refresh will not be executed until the bus mastership is acquired. This LSI has the

REFOUT pin to request the bus while waiting for refresh execution. For REFOUT pin function

selection, see section 19, Pin Function Controller (PFC). This LSI continues to assert

REFOUT

(low level) until the bus is acquired.

On receiving the asserted

REFOUT signal, the external device must negate the BREQ signal and

return the bus. If the external bus does not return the bus for a period longer than the specified

refresh interval, refresh cannot be executed and the SDRAM contents may be lost.

If a new refresh request occurs while waiting for the previous refresh request, the previous refresh

request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus

mastership occupation must be prevented from occurring.

If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is

completed.

R5F72115D160FPV Datasheet(PDF) 293 Page - Renesas Technology Corp