R5F72115D160FPV datasheet(297/1228 Pages) RENESAS

297 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 273 of 1200

REJ09B0344-0200

• Setting for Area 3

Burst read/single write (burst length 1):

Data Bus Width

CAS Latency

Access Address

External Address Pin

16 bits

H'FFFC5440

H'0000440

H'FFFC5460

H'0000460

Burst read/burst write (burst length 1):

Data Bus Width

CAS Latency

Access Address

External Address Pin

16 bits

H'FFFC5040

H'0000040

H'FFFC5060

H'0000060

Mode register setting timing is shown in figure 8.29. A PALL command (all bank pre-charge

command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An

MRS command (mode register write command) is finally issued. Idle cycles, of which number is

specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the

first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,

are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which

number is one or more, are inserted between the MRS and a command to be issued next.

It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after

power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse

width of the reset signal is longer than the idle time, mode register setting can be started

immediately after the reset, but care should be taken when the pulse width of the reset signal is

shorter than the idle time.

R5F72115D160FPV Datasheet(PDF) 297 Page - Renesas Technology Corp