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R5F72115D160FPV Datasheet(PDF) 301 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 301 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 277 of 1200
REJ09B0344-0200
• Deep power-down mode
The low-power SDRAM supports deep power-down mode as a low-power consumption mode.
In the partial self-refresh function, self-refresh is performed on a specific area. In deep power-
down mode, self-refresh will not be performed on any memory area. This mode is effective in
systems where all of the system memory areas are used as work areas.
If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to
1, the low-power SDRAM enters deep power-down mode. If the RMODE bit is cleared to 0, the
CKE signal is pulled high to cancel deep power-down mode. Before executing an access after
returning from deep power-down mode, the power-up sequence must be re-executed.
Tpw
Tp
Tdpd
Trc
Hi-Z
Trc
Trc
Trc
Trc
CK
CKE
A25 to A0
CSn
RD/
WR
RASL
DQMxx
D15 to D0
BS
DACKn*2
A12/A11*1
CASL
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.31 Deep Power-Down Mode Transition Timing



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