R5F72115D160FPV datasheet(304/1228 Pages) RENESAS

304 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 280 of 1200

REJ09B0344-0200

8.5.8

SRAM Interface with Byte Selection

The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin

(

WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte

selection pins, such as UB and LB.

When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM

interface with byte selection is the same as that for the normal space interface. While in read

access of a byte-selection SRAM interface, the byte-selection signal is output from the

WEn pin,

which is different from that for the normal space interface. The basic access timing is shown in

figure 8.33. In write access, data is written to the memory according to the timing of the byte-

selection pin (

WEn). For details, please refer to the Data Sheet for the corresponding memory.

If the BAS bit in CSnWCR is set to 1, the

WEn pin and RD/WR pin timings change. Figure 8.34

shows the basic access timing. In write access, data is written to the memory according to the

timing of the write enable pin (RD/

WR). The data hold timing from RD/WR negation to data write

must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 8.35 shows the access

timing when a software wait is specified.

R5F72115D160FPV Datasheet(PDF) 304 Page - Renesas Technology Corp