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R5F72115D160FPV Datasheet(PDF) 303 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 303 Page - Renesas Technology Corp

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Section 8 Bus State Controller (BSC)
Rev. 2.00 May. 08, 2008 Page 279 of 1200
REJ09B0344-0200
Note:
*
When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
CK
A25 to A0
RD
D15 to D0
DACKn*
Note: * The waveform for DACKn is when active low is specified.
WAIT
CSn
T1
Tw
Tw
TB2
Twb
TB2
Twb
TB2
Twb
T2
RD/
WR
BS
Figure 8.32 Burst ROM Access Timing (Clock Asynchronous)
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)



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