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R5F72115D160FPV Datasheet(PDF) 295 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 295 Page - Renesas Technology Corp |
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295 / 1228 page  Section 8 Bus State Controller (BSC) Rev. 2.00 May. 08, 2008 Page 271 of 1200 REJ09B0344-0200 (11) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel power-down mode. Figure 8.28 shows the access timing in power-down mode. Tnop Power-down Tr Tc1 Td1 Tde Tap Power-down CK CKE A25 to A0 CSn RD/ WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.28 Power-Down Mode Access Timing |
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