R5F72115D160FPV datasheet(323/1228 Pages) RENESAS

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Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 299 of 1200

REJ09B0344-0200

Section 9 Direct Memory Access Controller (DMAC)

The DMAC can be used in place of the CPU to perform high-speed transfers between external

devices that have DACK (transfer request acknowledge signal), external memory, on-chip

memory, memory-mapped external devices, and on-chip peripheral modules.

9.1

Features

• Number of channels: Eight channels (channels 0 to 7) selectable

Four channels (channels 0 to 3) can receive external requests.

• 4-Gbyte physical address space

• Transfer data length is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes

(longword

× 4)

• Maximum transfer count: 16,777,216 transfers (24 bits)

• Address mode: Dual address mode and single address mode are supported.

• Transfer requests

⎯ External request

⎯ On-chip peripheral module request

⎯ Auto request

The following modules can issue on-chip peripheral module requests.

⎯ Eight SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, and

two CMT sources

• Selectable bus modes

⎯ Cycle steal mode (normal mode and intermittent mode)

⎯ Burst mode

• Selectable channel priority levels: The channel priority levels are selectable between fixed

mode and round-robin mode.

• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-

data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to

the CPU when half of the initially specified DMA transfer is completed.

• External request detection: There are following four types of DREQ input detection.

⎯ Low level detection

⎯ High level detection

⎯ Rising edge detection

⎯ Falling edge detection

R5F72115D160FPV Datasheet(PDF) 323 Page - Renesas Technology Corp