R5F72115D160FPV datasheet(321/1228 Pages) RENESAS

321 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 297 of 1200

REJ09B0344-0200

peripheral bus (the example in figure 8.41 is for 4 × B

φ). Therefore, when Bφ:Pφ is 4:1, data is

transferred from the I bus to the peripheral bus in time (1+m) × B

φ, where m = 0 to 3 periods.

Note that the relationship between the timing with which the data appears on the I bus and the P

rising edge depends on the program execution state. In figure 8.41, since n = 0 and m = 3, the

access time will be 2 × I

φ + 4 × Bφ + 2 × Pφ.

C bus

I bus

Peripheral bus

(2+n) × I

(1+m) × B

2 × P

Figure 8.41 Internal Peripheral I/O Register Timing when I

φ:Bφ:Pφ = 4:4:1

Figure 8.42 shows an example of the write timing to the peripheral bus when the relationship

between the clocks is I

φ:Bφ:Pφ = 4:2:1. Although transfers from the C bus to the peripheral bus

are performed the same way for write, for read, the value read from the peripheral bus must be

transferred to the CPU. Although the transfers from the peripheral bus to the I bus and from the I

bus to the C bus are all performed on the corresponding bus clock rising edge, since I

φ ≥ Bφ ≥ Pφ,

(2 + 1) × I

φ periods are actually required. In the example in figure 8.42, since n = 1, m = 1, and i =

1, the access period will be 3 × I

φ + 2 × Bφ + 2 × Pφ + 3 × Iφ.

C bus

I bus

Peripheral bus

(2+n) × I

(1+m) × B

(2+I) × I

2 × P

Figure 8.42 Internal Peripheral I/O Register Timing when I

φ:Bφ:Pφ = 4:2:1

R5F72115D160FPV Datasheet(PDF) 321 Page - Renesas Technology Corp