R5F72115D160FPV datasheet(317/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 293 of 1200

REJ09B0344-0200

8.5.11

Bus Arbitration

The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus

mastership after receiving a bus request from another device.

Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released

immediately after receiving a bus request when a bus cycle is not being performed. The release of

bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even

when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be

performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot

be immediately determined whether or not bus mastership has been released by looking at the

CSn

signal or other bus control signals. The states that do not allow bus mastership release are shown

below.

1. Between the read and write cycles of a TAS instruction, or 64-bit transfer cycle of an FMOV

instruction

2. Multiple bus cycles generated when the data bus width is smaller than the access size (for

example, between bus cycles when longword access is made to a memory with a data bus

width of 8 bits)

3. 16-byte transfer by the DMAC

4. Setting the BLOCK bit in CMNCR to 1

Moreover, by using DPRTY bit in CMNCR, whether the bus mastership request is received or not

can be selected during DMAC burst transfer.

The LSI has the bus mastership until a bus request is received from another device. Upon

acknowledging the assertion (low level) of the external bus request signal

BREQ, the LSI releases

the bus at the completion of the current bus cycle and asserts the

BACK signal. After the LSI

acknowledges the negation (high level) of the

BREQ signal that indicates the external device has

released the bus, it negates the

BACK signal and resumes the bus usage.

With the SDRAM interface, all bank pre-charge commands (PALLs) are issued when active banks

exist and the bus is released after completion of a PALL command.

The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state

synchronized with the rising edge of CK. The bus mastership enable signal is asserted 0.5 cycles

after the above timing, synchronized with the falling edge of CK. The bus control signals (

BS,

CSn, RASL, CASL, CKE, DQMxx, WEn, RD, and RD/WR) are placed in the high-impedance

state at subsequent rising edges of CK. Bus request signals are sampled at the falling edge of

CKIO. Note that CKE,

RASL, and CASL can continue to be driven at the previous value even in

the bus-released state by setting the HIZCNT bit in CMNCR.

R5F72115D160FPV Datasheet(PDF) 317 Page - Renesas Technology Corp

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