R5F72115D160FPV datasheet(320/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 296 of 1200

REJ09B0344-0200

and then executes a SLEEP instruction. The code must, however, perform a dummy read of the

STBCR register before executing the SLEEP instruction. If the dummy read is not performed, the

CPU will execute the SLEEP instruction before the STBY bit is set to 1, and the system will not

switch to the intended software standby mode, but rather will switch to sleep mode. The dummy

read of the STBCR register is required to wait for the write to the STBY bit to complete.

In other cases as well, application code should perform a dummy read of the same register after a

to assure that the changes due to internal register writes are reflected when the following

instructions are executed as in this example.

The table below lists the number of access cycles required for CPU accesses to the on-chip

peripheral module registers.

Table 8.20

On-Chip Peripheral Module Register Access Cycle Counts

Access Cycles

Write

(2+n)

× Iφ + (1+m) × Bφ + 2 × Pφ

Read

(2+n)

× Iφ + (1+m) × Bφ + 2 × Pφ + (2+I) × Iφ

Note:

These are the numbers of cycles when the instruction is executed from internal ROM or

internal RAM.

When I

φ:Bφ is 1:1; n = 0, I = 0

When I

φ:Bφ is 2:1; n = 0 or 1, I = 1

When I

φ:Bφ is 4:1; n = 0 to 3, I = 2

When I

φ:Bφ is 8:1; n = 0 to 7, I = 2

When B

φ:Pφ is 1:1; m = 0

When B

φ:Pφ is 2:1; m = 0 or 1

When B

φ:Pφ is 4:1; m = 0 to 3

Note that n and m depend on the internal execution state.

This product adopts synchronized logic and has a hierarchical bus structure. Data input and output

for each of the busses is synchronized with the rising edge of the I

φ clock for the C bus, the Bφ

clock for the I bus, and the P

φ clock for the peripheral bus.

Figure 8.41 shows an example of the write timing to the peripheral bus when the relationship

between the clocks is I

φ:Bφ:Pφ = 4:4:1. Data is output in synchronization with Iφ to the C bus, to

which the CPU is connected. When I

φ:Bφ is 1:1, 2 × Iφ + Bφ periods are required for data

transfers from the C bus to the I bus. For transfers from the I bus to the peripheral bus when B

φ:Pφ

is 4:1, since there are four clock cycles during a single P

φ clock period, the timing with which the

data is placed on the peripheral bus is as follows: there are four timings for P

φ × 1, and up to 4 Bφ

periods are required for the P

φ rising edge, which is the timing for transfers from the I bus to the

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