EP4CE40 datasheet(220/488 Pages) ALTERA

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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

If you configure a master device with an SFL design, the master device enters user

mode even though the slave devices in the multiple device chain are not being

configured. The master device enters user mode with a SFL design even though the

CONF_DONE

signal is externally held low by the other slave devices in chain.

Figure 8–29 shows the JTAG configuration of a single Cyclone IV device with a SFL

design.

ISP of the Configuration Device

In the second stage, the SFL design in the master device allows you to write the

configuration data for the device chain into the serial configuration device with the

Cyclone IV device JTAG interface. The JTAG interface sends the programming data

for the serial configuration device to the Cyclone IV device first. The Cyclone IV

device then uses the ASMI pins to send the data to the serial configuration device.

Figure 8–29. Programming Serial Configuration Devices In-System Using the JTAG Interface

Notes to Figure 8–29:

(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL for AS

configuration schemes, refer to Table 8–3 on page 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–9. Connect

the MSEL pins directly to VCCA or GND.

(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. The VIO must match the VCCA of the

device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. When using the

ByteBlasterMV download cable, this pin is a no connect. When using USB-Blaster, ByteBlaster II, and EthernetBlaster

cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.

(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.

(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(6) Power up the VCC of the EthernetBlaster, ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V VCCA supply.

Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable.

The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from

the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.

(7) Connect the series resistor at the near end of the serial configuration device.

(8) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions

as DATA[1] pin in AP and FPP modes.

(9) Resistor value can vary from 1 k

Ω to 10 kΩ.

(10) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for

DCLK

nCE (4)

MSEL[ ]

nCONFIG

CONF_DONE

VCCA

VCCA (6)

GND

VCCIO (1)

GND

VCCIO (1)

(2)

(10)

VCCA

(9)

1 k

10 k

nSTATUS

Pin 1

Download Cable 10-Pin Male

Header (Top View)

GND

TCK

TDO

TMS

TDI

CLKUSR

GND

VIO (3)

Cyclone IV Device

nCEO

N.C. (5)

DCLK

DATA[0]

nCSO (8)

ASDO (8)

DCLK

DATA

nCS

ASDI

Serial Configuration

Device

VCCIO (1)

10 k

Serial

Flash

Loader

Ω (7)

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