EP4CE40 datasheet(219/488 Pages) ALTERA

219 / 488 page

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

8–55

Configuration

May 2013

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Programming Serial Configuration Devices In-System with the JTAG Interface

Cyclone IV devices in a single- or multiple-device chain support in-system

programming of a serial configuration device with the JTAG interface through the SFL

design. The intelligent host or download cable of the board can use the four JTAG pins

on the Cyclone IV device to program the serial configuration device in system, even if

the host or download cable cannot access the configuration pins (DCLK, DATA, ASDI, and

nCS

pins).

The SFL design is a JTAG-based in-system programming solution for Altera serial

configuration devices. The SFL is a bridge design for the Cyclone IV device that uses

their JTAG interface to access the EPCS JTAG Indirect Configuration Device

Programming (.jic) file and then uses the AS interface to program the EPCS device.

Both the JTAG interface and AS interface are bridged together inside the SFL design.

In a multiple device chain, you must only configure the master device that controls

the serial configuration device. Slave devices in the multiple device chain that are

configured by the serial configuration device do not have to be configured when

using this feature. To successfully use this feature, set the MSEL pins of the master

device to select the AS configuration scheme (Table 8–3 on page 8–8, Table 8–4 on

page 8–8, and Table 8–5 on page 8–9). The serial configuration device in-system

programming through the Cyclone IV device JTAG interface has three stages, which

are described in the following sections:

■

“Loading the SFL Design”

■

“ISP of the Configuration Device” on page 8–56

■

“Reconfiguration” on page 8–57

Loading the SFL Design

The SFL design is a design inside the Cyclone IV device that bridges the JTAG

interface and AS interface with glue logic.

The intelligent host uses the JTAG interface to configure the master device with a SFL

design. The SFL design allows the master device to control the access of four serial

configuration device pins, also known as the Active Serial Memory Interface (ASMI)

pins, through the JTAG interface. The ASMI pins are serial clock input (DCLK), serial

data output (DATA), AS data input (ASDI), and active-low chip select (nCS) pins.

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