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UM0434 Datasheet(PDF) 102 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 102 Page - STMicroelectronics |
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102 / 390 page ![]() UM0434 Register model 103/391 4.19 Parallel signature unit registers To support applications requiring system integrity checking during operation, the e200z3 provides a Parallel Signature unit to monitor the CPU data read and data write AHB buses and to accumulate a pair of 32-bit MISR signatures of the data values transferred over these buses. The primitive polynomial used is P(X)=1+X10+X30+X31+X32. Values are accumulated based on an initially programmed seed value and are qualified based on active byte lanes of the data read and data write buses ( p_d_hrdata[63:0], p_d_hwdata[63:0]) as indicated via the p_d_hbstrb[7:0] signals. Inactive byte lanes use a value of all zeros as input data to the MISRs. Refer to Table 170 for active byte lane information. If a transfer error occurs on any accumulated read data, the returned read data is ignored, a value of all zeros is used instead, and the error is logged. Errors occurring on data writes are not logged, since the data driven by the CPU is valid. The unit can be independently enabled for read cycles and write cycles, allowing for flexible usage. Software can also control accumulation of software-provided values via a pair of update registers. In addition, there is a counter for software to monitor the number of beats of data compressed. Updates are performed when the parallel signature registers are initialized, when a qualified bus cycle is terminated, when a software update is performed via a high or low update register, and when the parallel signature high or low registers are written with an mtdcr instruction. Note: Updates due to qualified bus transfers are suppressed for the duration of a debug session. SRR0 Unaffected 1 SRR1 Unaffected 1 SVR 3 — TBL Unaffected 1 TBU Unaffected 1 TCR 0x0000_0000 TLB0CFG– TLB1CFG — TSR Undefined on power-on reset; otherwise, 0x(0b00||WRS)000_0000 USPRG0 Unaffected 1 XER 0x0000_0000 1. Undefined on m_por assertion, unchanged on p_reset_b assertion. 2. For CTXCR 0 only, others unaffected. 3. Read-only register. Table 90. Reset settings for e200z3 resources (continued) Resource System reset setting |
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