UPD78044F datasheet(17/472 Pages) NEC

17 / 472 page

User’s Manual U16504EE1V1UD00

Figure 12-12:

A/D Conversion End Interrupt Request Generation Timing....................................... 194

Figure 12-13:

D/A Converter Mode Register (DAM0) Format.......................................................... 195

Figure 13-1:

Block Diagram of SIO30 ............................................................................................ 197

Figure 13-2:

Format of Serial Operation Mode Register (CSIM30) ............................................... 199

Figure 13-3:

Format of Serial Operation Mode Register (CSIM30) ............................................... 200

Figure 13-4:

Format of Serial Operation Mode Register (CSIM30) ............................................... 201

Figure 13-5:

Timing of Three-wire Serial I/O Mode........................................................................ 202

Figure 14-1:

Block Diagram of SIO31 ............................................................................................ 206

Figure 14-2:

Format of Serial Operation Mode Register (CSIM31) ............................................... 208

Figure 14-3:

Format of Serial Mode Switch Register (SIOSWI)..................................................... 209

Figure 14-4:

Format of Serial Operation Mode Register (CSIM31) ............................................... 210

Figure 14-5:

Format of Serial Operation Mode Register (CSIM31) ............................................... 211

Figure 14-6:

Format of Serial Mode Switch Register (SIOSWI)..................................................... 212

Figure 14-7:

Format of Serial Operation Mode Register (CSIM31) ............................................... 213

Figure 14-8:

Format of Serial Mode Switch Register (SIOSWI)..................................................... 214

Figure 14-9:

Timing of Three-wire Serial I/O Mode........................................................................ 215

Figure 14-10:

Timing of Two-wire Serial I/O Mode .......................................................................... 215

Figure 15-1:

Block Diagram of UART ............................................................................................ 217

Figure 15-2:

Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) ................... 220

Figure 15-3:

Format of Asynchronous Serial Interface Status Register (ASIS0) ........................... 222

Figure 15-4:

Format of Baud Rate Generator Control Register (BRGC0) (1/2)............................. 223

Figure 15-5:

Register Settings ....................................................................................................... 225

Figure 15-6:

Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2) ................... 226

Figure 15-7:

Format of Asynchronous Serial Interface Status Register (ASIS0) ........................... 228

Figure 15-8:

Format of Baud Rate Generator Control Register (BRGC0) (1/2)............................. 229

Figure 15-9:

Error Tolerance (when k = 0), including Sampling Errors.......................................... 232

Figure 15-10:

Format of Transmit/Receive Data in Asynchronous Serial Interface......................... 233

Figure 15-11:

Timing of Asynchronous Serial Interface Transmit Completion Interrupt .................. 235

Figure 15-12:

Timing of Asynchronous Serial Interface Receive Completion Interrupt ................... 236

Figure 15-13:

Receive Error Timing................................................................................................. 237

Figure 16-1:

Data Frame ............................................................................................................... 241

Figure 16-2:

Remote Frame .......................................................................................................... 241

Figure 16-3:

Data Frame ............................................................................................................... 242

Figure 16-4:

Arbitration Field/Standard Format Mode ................................................................... 242

Figure 16-5:

Arbitration Field/Extended Format Mode................................................................... 243

Figure 16-6:

Control Field (Standard Format Mode)...................................................................... 244

Figure 16-7:

Control Field (Extended Format Mode) ..................................................................... 244

Figure 16-8:

Data Field .................................................................................................................. 245

Figure 16-9:

CRC Field .................................................................................................................. 245

Figure 16-10:

ACK Field .................................................................................................................. 246

Figure 16-11:

End of Frame............................................................................................................. 246

Figure 16-12:

Interframe Space/Error Active ................................................................................... 247

Figure 16-13:

Interframe Space/Error Passive ................................................................................ 247

Figure 16-14:

Error Frame ............................................................................................................... 248

Figure 16-15:

Overload Frame ........................................................................................................ 249

Figure 16-16:

Nominal Bit Time (8 to 25 Time Quanta) ................................................................... 255

Figure 16-17:

Adjusting Synchronization of the Data Bit ................................................................. 256

Figure 16-18:

Bit Synchronization.................................................................................................... 257

Figure 16-19:

Transmission State Shift Chart.................................................................................. 258

Figure 16-20:

Reception State Shift Chart ....................................................................................... 259

Figure 16-21:

Error State Shift Chart ............................................................................................... 260

Figure 16-22:

Structural Block Diagram........................................................................................... 261

Figure 16-23:

Connection to the CAN Bus ...................................................................................... 262

Figure 16-24:

Transmit Message Definition Bits ............................................................................. 266

Figure 16-25:

Transmit Identifier ..................................................................................................... 267

Figure 16-26:

Transmit Data ........................................................................................................... 268

Figure 16-27:

Control bits for Receive Identifier ............................................................................. 271

Figure 16-28:

Receive Status Bits (1/2) .......................................................................................... 272

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